I am using AD9625BBPZ-2 in my board. In the first power on test I found the IC is over heated. Kindly suggest possible causes for this over heating.
These numbers are in-line with the thermal simulation data in table 7 of the datasheet which shows 11.5 degrees/C per W for Tja. You are seeing about 45C increase from 27 ambient which is roughly 11.5 C/W increase if we assume the full data rate operation. For a thinner board (4 layers), Tja could be higher. Please review this table as well as Figure 44 which shows the VMON output voltage across temperature for the Junction temp.
Please let me know if this does not fully answer your question or there are more details that you need.
The AD9625BBPZ will consume up to 3.8W in full sample rate mode of 2.5GSPS. The case temperature can be relatively hot. Can you elaborate on why you think that the temperature is exceeding the expectations of the datasheet for power and temperature? Can you provide the thermal diode voltage reading for the AD9625BBPZ in your use case? Can you measure the case temperature at the top of the package? Do you know the current consumption for each domain that you can share?
Thanks for your response.
Get the Temperature value measured by thermistor at the first 10 mins in first power on.
The AD9625 ADC is working fine only the heat dissipation is more. As u said the heat dissipation is with in the limit, I started configuring the ADC. The PLL got locked & ADC conversion is happening.
Without any ADC input the ADC digital count of +/- 16 has been observed. What will be the cause for this more count value ?
First, please be sure to issue a reset to the AD9625 using a value of 0x3C --> 0x00.
In addition, a gain calibration is performed in the background and the threshold default is -5dBFS. If you do not have a signal of that amplitude, the calibration will not run and may cause this issue that you are seeing. Please review the details of this operation below and adjust the threshold if needed.
For best performance, the AD9625 needs an input signal to perform internal calibration. This signal needs to exceed a set threshold that is established through register settings. The threshold prohibits background calibration updates for small signal amplitudes. The threshold for gain calibration is enabled by default to -5dBFS.
The absolute value of every sample is accumulated to produce an average voltage estimate.
When the calibration has run for its predetermined number of samples, the voltage estimate is compared tothe data set threshold. If the voltage estimate is greater than thethreshold, the calibration coefficients update; otherwise, no update occurs.
The threshold registers are all 16-bit registers loaded via the SPI one byte at a time. The threshold values range from 0 to 16,384, corresponding to a voltage range of 0.0 V to 1.2 V (full scale).
The calibration threshold range is 0 to 16,384 (0x00 to 0x4000, hexadecimal) and represents the average magnitude of the input. For example, to set the threshold so that a −6 dBFS input sine wave sits preciselyat the threshold requires a threshold setting of 16,384 × 10 ^(-6/20) x 2/pi > 5228 The registers for this threshold are located in 0x10D (LSB) and 0x10E (MSB). The details of these registers can be found in the datasheet in the memory map section.
I am getting a noise floor of -95dBFS/Hz in AD9625-2.0 ADC part. In data sheet it is mentioned that -149dBFS can be achieved. I am using a sampling clock of 1.2GHz.
Kindly suggest how can I reduce my noise floor ?
The NSD of -149dBFS/Hz for AD9625-2.0 is rated for 2,000MSPS. Sampling at 1200MSPS will be slightly lower by about -2dBFS/Hz. However, it sounds like you are substantially off this mark in performance.
Please be sure that you are using the 4L output mode for 1200MSPS operation.
Also, can you confirm that your captured data is correct in your FPGA such that you do not have link errors or lane alignment problems within the JESD204B receiver?
If necessary, please email me directly if you cannot discuss details of your specific system.
Retrieving data ...