I wish to synchronize two AD9910 using ADCLK846, but I'm thinking of designing my own PCB instead of the analog devices manufactured evaluation board.
I have two AD9910 (one master, one slave) so I will be using only OUT_0/Out_0_BAR and OUT_1/OUT_1_BAR. my questions are:
1) Required length and width of traces to match 50 ohm impedance, considering I'm using 1GHZ ref clock, which gives me 31.25Mhz sync_out signals.
2) Can I directly apply the LVDS signal of my master ad9910 into ADCLK ( DC offset 1.2v, 400mv p-p). I see there are dc block capacitors in series in the CLK/CLK_BAR path, which will block the DC of LVDS, should I exclude these in my design?
3) How do I set the DC offset to 1.2V using the VREF.