AnsweredAssumed Answered

Max sampling rate for AD9361 AuxADC?

Question asked by gaelen on Feb 10, 2015
Latest reply on Feb 11, 2015 by tlili

Hello,

The AD9361 documentation suggests that the max AuxADC clock_frequency = BBPLL_frequency and minimum AuxADC decimation is 256. Does this translate to a max. achievable sampling rate of BBPLL_frequency/256 for the AuxADC?

 

Thanks
Gaelen

Outcomes