Hello,

The AD9361 documentation suggests that the max AuxADC clock_frequency = BBPLL_frequency and minimum AuxADC decimation is 256. Does this translate to a max. achievable sampling rate of BBPLL_frequency/256 for the AuxADC?

Thanks

Gaelen

Hello,

The AD9361 documentation suggests that the max AuxADC clock_frequency = BBPLL_frequency and minimum AuxADC decimation is 256. Does this translate to a max. achievable sampling rate of BBPLL_frequency/256 for the AuxADC?

Thanks

Gaelen

That is correct. With AuxADC Clock Divider set to 1 and AuxADC Decimation at 0 the effective clock rate is BBPLL Frequency/256. Note that AuxADC output word readback speed will be governed by the speed of the SPI clock you are using.