I have just made a PLL circuit as in the AD650 datasheet revision E, page 17 figure 22. I'm using the LF411 instead of the obsolete AD509 (a new updated revision would be nice) and SD211DE as the DMOSFET. My problem is that the SD211DE don't survive very long. Accordning to the datasheet from LINEARSYSTEMS the maximum voltage between Source and Drain should not exceed 15V but with the suggested construction in the datasheet it will be 18V when Q2 (of the 7474) goes high. Have I missed something or how could the construction be customized to the maximum of 15V between Source and Drain?
Looking forward to your ideas,