I do not understanding about this figure 52.
Would you kindly help me explain it. Specifically PSET
I have branched this to a new topic to help others searching for it.
what you see here is the profile of ADM1278 current limit threshold during a power up event.
There are three factors controlling the current limit on ADM1278, voltage on ISET pin (this allows you to fine adjust the current limit without the need to change the Rsense), Voltage on ISTART pin (controlling the current limit before PWRGD), and PSET (used to control the constant power in the external MOS).
user has the ability to adjust all three of them to suit their particular application, each of the have a slightly different profile as shown in the diagram, the lowest value of the three will determine the actual current limit of the ADM1278.
The actual current limit of the ADM1278 is shown by the red curve, as you can see it always takes the lowest value of the three other curves.
From the start, VOUT is 0V. There is a large voltage drop across the MOSFET (VIN-VOUT), to keep the power in the MOS constant, the current needs to be very low, thus the PSET at the very start is very low, which dominates the device current limit. As the load capacitance is charged up, VOUT rises, less voltage across the FET, more current are allowed, so PSET rises.Once PSET crosses ISTART value, ISTART will start to dominate and limits the current limit. ISTART is to make sure the FET is protected during slow start up due to capacitor placed on the GATE pin, see datasheet for details. ISTART will be disabled once VOUT has reached power good level, at which point the current limit will jump from ISTART to keep following PSET. This continuous once PSET crosses ISET and eventually ISET will control the current limit once the load is fully powered up.
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