First time posting on this discussion forum so please bear with me. What I am trying to do is to use this FMCOMMS2 reference design for the ZC706 dev. kit to interface with Matlab/Simulink in order to pass I/Q to a AD9361. However, instead of using a FMC board I would like to route the data to and from another physical layer so that i can pipe it into an external platform with a 9361. I am looking at the HDL design and I want to make sure that I have identified the appropriate place to intercept the data paths to divert them from the axi_9361 block to this alternate driver. I would like the Matlab/Simulink/IIO/Linux portion of the design to remain relatively untouched and have the HDL changes be pretty much invisible to the user. Can someone please give this concept a sanity check and let me know if I am looking at this design correctly from a data flow perspective?
For TX out of the ZC706 I have to interface to the util_dac_unpack and read channel data from the 4 dac_data_# ports according to what is described in the DAC Interface section of ADI Reference Designs HDL User Guide [Analog Devices Wiki].
For RX into the ZC706 I will be writing data to the util_adc_pack chan_data_# ports according to what is ADC interface section of that above link.
Part of what is throwing me off is the nomenclature of ADC and DAC with respect to TX and RX. If you need to know a bit more about what I am trying to do or it is unclear let me know and I will try to explain. I appreciate your help and time. Thanks!