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Generate 10 MHz Sine wave frequency locked to 1 pps

Question asked by Lionelwallace Employee on Feb 9, 2015
Latest reply on Feb 9, 2015 by KennyG

I received this inquiry regarding an IEEE 1588 application:


  • Need to generate a 10 MHz sine wave that will be frequency locked with 1 pps (pule per second) signal
  • Frequency source will be low jitter, FPGA output
    • Frequency can be adjusted as necessary
  • FPGA can generate 1 pps output.  This will be a digital output
  • FPGA can generate a 10 MHz output (or other convenient frequency) to use for conversion to sine wave.  Also a digital output
  • Would like to convert 10 MHz digital output from FPGA to 10 MHz sine way with spurs < -50dBc
    • Not sure simple low pass filtering can achieve this
  • Considering DDS to generate sine wave instead
    • AD9833, AD5932, AD9834



  • If the clock input to the DDS is synchronized with my 1 pps signal, will the DDS output since be in sync as well?
    • If not, can phase sync be achieved using DDS?
  • Can -50 dBc be achieved at 10 MHz with a DDS clocked as low as 25 MHz (i.e. AD9833)
    • If not, what would be the minimum frequency?
  • Any other ideas on how to create a clean pure sine wave (-50 dBc) locked to the 1 pps inexpensively?
    • Considered using PLL, but VCOs inflate the solution cost