I initialized BF609 CGU to have 500 MHZ CCLK, 250MHZ SYSCLK, 125MHZ S0CLK and S1CLK and 125 MHZ DCLK. CLOCKIN is 25 MHZ from clock synthizer default output. I m seeing whole assignments are correct in registers captured by debug view. However when i check CGU status register i m seeing DIVERR as set which indicates CSEL divider is greater than SYSCLK devider. This i not correct because i m seeing SYSCLK devider is 2 while CSEL is 1. I m not seeing this error when i use idi_pwr_init from example mode change project of BF609-EZKIT library however this driver does not assign my values into registers. Since function boady is not available i could not understand the root cause. I checked backfin device driver reference manual but not have enough time to read line by line.
my pseudo code is like below:
CLKIN=25MHZ MSEL=20, DF=0 => PLLCLK=500 MHZ, CSEL=1 (500), SSEL=2 (250), SOSEL=2 (125), S1SEL=2 (125), DSEL=4 (125), OSEL=50 (10)
while (PLLON!=1,PLLLCK!=1, CLKALGN!=0) wait
while (PLLLCK!=1, CLKALGN!=0) wait
I m generating OUTCLK as 500/50=10 MHZ and will check it on the oscilloscope to be able to understand whether PLL works correctly or not.
Could you please provide an example code to init CGU for above values?
Furthermore; when i read reference manual i m seeing indications like CGU_CTL.MSEL. is it possible to reach this registers fields like this in project?