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Help with ADC data stream from PL to PS. Whats wrong with this design?

Question asked by Shan.sk on Feb 9, 2015
Latest reply on Feb 11, 2015 by CsomI

Hi,

 

I'm trying to connect the AD7961 (5MHz) I designed tADC to Zedboard. I got the AD7961 no-os driver module from the AD7961 example project at AD-WIKI site which has the following interface:

 

module AD7961

    (

        input           m_clk_i,                    // 100 MHz Clock, used for tiing

        input           fast_clk_i,                 // Maximum 300 MHz Clock, used for serial transfer

        input           reset_n_i,                  // Reset signal, active low

        input   [ 3:0]  en_i,                       // Enable pins input

        input           d_pos_i,                    // Data In, Positive Pair

        input           d_neg_i,                    // Data In, Negative Pair

        input           dco_pos_i,                  // Echoed Clock In, Positive Pair

        input           dco_neg_i,                  // Echoed Clock In, Negative Pair

        output  [ 3:0]  en_o,                       // Enable pins output

        output          cnv_pos_o,                  // Convert Out, Positive Pair

        output          cnv_neg_o,                  // Convert Out, Negative Pair

        output          clk_pos_o,                  // Clock Out, Positive Pair

        output          clk_neg_o,                  // Clock Out, Negative Pair

        output          data_rd_rdy_o,              // Signals that new data is available

        output  [15:0]  data_o                      // Read Data

    );

I designed custom IP using AXI4Stream interface and in the default code I replaced the commented line with the assignment to adc_data_reg which gets the value of adc_data_out wire from the ad7961 module.

// Streaming output data is read from FIFO     

     always @( posedge M_AXIS_ACLK )                

     begin                                          

       if(!M_AXIS_ARESETN)                          

         begin                                      

           stream_data_out <= 1;                    

         end                                        

       else if (tx_en)// && M_AXIS_TSTRB[byte_index]

         begin                                      

          // stream_data_out <= read_pointer + 32'b1;

          stream_data_out <= adc_data_reg;

         end                                        

     end   

And here's my block design:

Capture18.PNG

I used the data_rd_rdy_out as a clock for the m00_axis and the fifo input. In the SDK I used the DMA to collect data in the DDR but when I check that data its not correct. Whats wrong with this design?

Could you please help me out?

 

Thanks.

 

Regards,

 

Shan

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