Does ADI have a product that supports MIPI splitting (4 lanes and 1 clock)?
One MIPI source should reach 2 MIPI receivers on the same time.
Any design idea is welcomed.
The MIPI D-PHY physical layers of the transmitter and receiver part perform all the termination for the MIPI CSI-2 transmissions. The MIPI D-PHY of the receiver needs to dynamically detect the mode of operation of the transmitter and then change its termination. The MIPI D-PHY specification is very specific in the value of the termination and the speed at which it changes.
If the receiver is not terminated correctly then the MIPI CSI-2 transmissions will be incredibly noisy and the video will not be able to be decoded. See MIPI D-PHY specification for more information.
Having a second receiver connected to the same MIPI CSI-2 stream would change the overall termination probably outside specification. It would also act like a massive stub injecting noise into the MIPI CSI-2 transmissions.
It may not be impossible to have a single MIPI CSI-2 transmitter connected to two MIPI CSI-2 receivers, but it would not be simple to implement. I strongly advise you against going down this path.
MIPI CSI-2 is designed to be a single transmitter connected to a single receiver. I would stongly advise you to use it this way.
I don't think so, but I'll check.
Sorry the answer is no. MIPI CSI-2 is designed to be a single Tx to a single Rx.
If the direction is unique, let's say from the source to a destinatin (display) is there a way to connect the source to 2 displays? if not, what is the reason/limitation?
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