I am currently using the ADV7511/AD7842 eval board to test a design. I am feeding it 4:2:2 video with a 2x clock at a 37.5MHz pixel rate (75MHz Clock). When I set the input to ID 3 the PLL does not lock (register 9E bit 4). If I set the input ID to 6 the PLL locks and is stable. Of course the video out is distorted and colors are distorted. Does the ADV7511 support pixel rates down to 37.5MHz? Are there any hardware or software changes that would make this more stable at the low clock frequency? (I have verified that Rext is the suggested 887Ω. I have also tested the same 37.5MHz pixel rate source an a working 75MHz pixel rate system and have found that the PLL is unable to lock. Other things tried include series resistors in the clock, data, and sync lines; terminating the clock line; and other clock sources.