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ADRF6601 PLL Reference and Phase  Freq Limits ?

Question asked by JimPennell on Nov 12, 2010
Latest reply on Nov 19, 2010 by JimPennell

   I want to use the ADRF6601 with a 10 MHz reference input freq.   I see the Spec claims a lower limit of 12 MHz.   Is this due to a concern about the rise/fall times of the reference clock ?


   If so, would a square wave 10 MHz reference input be good ?


  Or, do I need to use the internal reference doubler to produce 20 MHz and then divide ?


  When I read the Spec, I do not find a parameter for the maximum phase comparator frequency.   I woule like to use 10MHz into the phase comparator, preferebly with a reference divide ratio of 1.


  What is the maximum allowable reference frequency into the phase comparator ?