I am using zedboard with fmcomms1. I am using the HDL reference design from the analogdevicesinc/hdl · GitHub

I was trying to understand how the clock is running between zedboard PL and fmcomms1. The port ref_clk which is clock of 30.3 MHz is routed to the AD9548 9548_REF_P pinin the fmcomms1. The dac_clk_in clock input on axi_ad9122 is 462.96 MHz and it is connected to the AD9523-1 DAC_DCO_P output port. The output clock from axi_ad9122 dac_out_p is connected to the AD9122 DAC_DCI_N input port. I don't know this clock frequency.

Can someone try to explain me how the fmcomms1 with dac 9122 works together with zedboard!?

I want to pump data with rate of 16 MHz inside the DAC. So does ti mean that my out put clock dac_out_p should be 16 MHz and should I change anything in the imput clock for axi_ad9122 or for referenc clock I provide to the fmcomms1 AD9548 !?

Please let me know if this is possible.

Regards,

Jet

Hi Jet,

Sorry for the late response, I just saw this open question.

The board has a 122.88Mhz VCXO on board. the 491.52Mhz is 4 times the 122.88MHz.

Or said another way, it's 122.88MHz times 24, divided by x where x is greater then 3 for sampling rate.

So you can get 2949.12 MHz as your multiplied reference and divide it by an integer to get the frequencies that are possible to get.

for x = 8 you get the 491.52MHz, for x = 12 you get 245.76MHz, for x = 29 you get 101.69MHz and so forth.

Charly