In ADV76xx series, Is there a case to lock the wrong RX-PLL during input of interlaced image?
In our verification environment, it looks like it is often the lock error occurs during input of interlaced image.
When the lock error occurs, PLL lock status is normal, but the image will be no output.
What the same time all of until the lock of RX PLL of ADV76xx series?
(In particular I've been focusing on the performance of the ADV7630.)