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Speeding up synthesis of ref-design

Question asked by tfabric on Feb 3, 2015
Latest reply on Feb 3, 2015 by rgetz

I know this is more like a Xilinx question.

I am debugging my zc706-fmcomms5 design, but every re-synthesis takes 2 hours (win 7-64 bit, I7-3630QM@2.4GHz and 8GB). I only make changes in a "small corner" of the design, so I was wondering if "out-out-context" setting could be enabled. But it is only the top level system.bd that allows me to do that. "Set as Out-of-Context Module..." is greyed for Verilog/vhdl files, and "Out-of-Context Settings..." are grayed for IP blocks. When generating output products, "out-of-context" setting only show the system.bd, but that is also greyed.

 

Any ideas ? or other suggestions ?

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