AnsweredAssumed Answered

AD9361 driver divide by zero

Question asked by rjhale on Feb 2, 2015
Latest reply on Feb 5, 2015 by rjhale

I think we are missing part of the initialization routines in our build.  We are calculating clock rate and when using the bb_pll rate find that it has not been initialized (all zeros) and that rate is used as a divider.   Please keep in mind we do not have a Xilinx in our design and have not include any of the AXI.. (Xilinx bus routines) in our build.

 

Thanks for the help.

 

RJ

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