I am using the EVAL_AD7961_FMCZ board to read values from the ADC into the Zedboard. I got the ADC verilog driver file from the Analog Devices WIKI project that uses AD7961 that has the following interface:
input m_clk_i, // 100 MHz Clock, used for tiing
input fast_clk_i, // Maximum 300 MHz Clock, used for serial transfer
input reset_n_i, // Reset signal, active low
input [ 3:0] en_i, // Enable pins input
input d_pos_i, // Data In, Positive Pair
input d_neg_i, // Data In, Negative Pair
input dco_pos_i, // Echoed Clock In, Positive Pair
input dco_neg_i, // Echoed Clock In, Negative Pair
output [ 3:0] en_o, // Enable pins output
output cnv_pos_o, // Convert Out, Positive Pair
output cnv_neg_o, // Convert Out, Negative Pair
output clk_pos_o, // Clock Out, Positive Pair
output clk_neg_o, // Clock Out, Negative Pair
output data_rd_rdy_o, // Signals that new data is available
output [15:0] data_o // Read Data
So making use of the AXI4Lite I have designed a hardware that reads and latches the value of data_o when the data_rd_rdy_o goes high. I debugged the hardware using ILA and the output wasn't as expected.
The first signal is the data_o (only last 16bits) and the second signal is the data_rd_rdy_o. The third one is where I latch the value of data_o. The data output looks strange as
- Looks like data keeps accumulating till the data_rd_rdy_o goes high but it suddenly accumulates to zero sometimes.
- The data output value is always zero or 21 (hex) no matter what input I give to the board.
Could some one please point out what could have gone wrong?
Heres my hardware setup :