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ADV7181D video clamping

Question asked by jerivera on Jan 30, 2015
Latest reply on Feb 2, 2015 by GuenterL

I'm processing a 525i NTSC RGB signal with embedded SOG using Component Processor. The signal comes from a SONY 3CCD camera. Following the ADV7181D we have an FPGA, followed by a ADV7341 video encoder. We use full 24bit 444 video encoding using 12bit DDR mode. The FPGA receives the 12 bit interleaved data and converts to 24 bit, which is fed directly to the AV7341, set to receive full 24 bit video. Our FPGA generates a genlock composite sync signal which is sent to the camera to lock the camera video to our system. We also send discrete HSYNC and VSYNC signals out from the FPGA to the input of the ADV7181D, and set the part to accept separate HSYNC and VSYNC synchronization (register 0x85, bits 5 and 4). When I use this method of synchronization our video output looks saturated and the black levels are too high. However when I change to using SOG instead, the video at the output look very close to the camera source. There seems to be a difference in the video clamping position or video gain settings when I change from external sync to SOG. The part states that clamping position is set automatically based on PRIM mode and video standard. I looked at the timing of the external HSYNC relative to the SOG HSYNC and they differ by about 1us. Given that the back porch time is about 5us and clamping is set to be about in the middle of that, I would expect that clamping will still be performed correctly when using external SYNC. What do you think is the cause of this brightness change when I change from external SYNC to SOG?

 

Jose Rivera

Lockheed Martin Orlando FL

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