I am trying to change reference design from tutorial AD-FMCOMMS1-EBZ Quick Start Guide on Xilinx FPGA Boards Without OS [Analog Devices Wiki] in vivado 2014.2 but I got some errors like this
[Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I2, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: system_i/axi_cpu_interconnect/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/s_axi_bvalid_INST_0_i_6.
I would like to remove hdmi and all cores that I do not needed for implementation of TxRx devices. I see that current design is made to support OS. Should I also change or modify axi_cpu_interconnect, after removing hdmi... and other cores that I do not need ? In this post I got some informations but I am still confused Getting streaming data from FMCOMM1-EBZ to ZedBoard
Also I do not understand how data is transferred from ARM to FPGA Logic -> DAC. In design I see adc_dma_wdata port but I could not get it where it is connected or from where it is getting data. Is data written into memory and adc_dma_wdata is mapped to that part of memory?
Sorry if questions are basic, but I am trying to understand how it is working. Feel free to send me suggestions on literature and etc
Thank you in advance on answers,