Please let me know the following questions about the AD9257.
1) Clock divider function to multiply the SYNC input. Is this correct?
2) "Input clock phase adjust" feature can be used to shift the clock and sampling phase to be input to the AD9257. Is this correct?
3) Can you provide document(block diagram, etc.) related to the operation overview regarding Clock divider and Input clock phase adjust
and the output clock generation circuit (Data rate multiplier)?