RevB data sheet recommended SPI initialization in Table 32 (page 47) shows values for Register 0x10 in steps 24, 25 & 26 that don't match up with the values set in Register 0x10 in steps 17 & 18. Are the values in steps 24, 25 & 26 correct?
You have found some errata in the data sheet. The values in steps 24, 25, and 26 do not comprehend the SYNC settings from steps 17 and 18. Thus, the entries for steps 24, 25, and 26 should be viewed with a mask of 0x0F, meaning the upper byte of those words depends on the SYNC settings. So, if you are making the DAC Master, you should have 0x7x, and Slave would be 0x5x, with x being the values given for the LVDS controller in steps 24, 25, and 26.
The sequence should be to enable the SYNC controller, verify lock, and then enable the LVDS controller.
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