Hi, I'm needing to modify the 9361 software to account for some crossed/inverted data lines on our custom hardware (i.e. most but not all LVDS pairs have the P side connected to the N pin and vice versa). I looked through the ad9361_pp_port_setup routine and associated registers, and had several questions:
1) Inverting DATA_CLK. It looks like I can invert DATA_CLK by either setting D0 on 0x010 (REG_PARALLEL_PORT_CONF_1) or by setting D5 on the SPI register controlling LVDS inversion (0x03E, REG_LVDS_INVERT_CTRL_2). Is one better than the other, or can I just pick one?
2) Setting registers for LVDS inversion. Table 24 of the register map (page 18 on my copy) talks about how to set bits to invert certain LVDS pairs, but the paragraph describing it is a little confusing. For example, I'm using 2R2T mode, so P1 is RX and P0 is TX. Lets say on my hardware that all the RX data line connections are crossed (all P pins from the 9361 are connected to N pins on the FPGA), RX DATA_CLK is crossed, and Rx Frame is not crossed.
If I'm reading correctly, the rx data lines are inverted by default, so no changes are needed. Rx frame is not inverted by default, so that should be fine too. The RX DATACLK is not inverted by default, so I would just set D5 to 1 on 0x03E / REG_LVDS_INVERT_CTRL_2 (or D0 in 0x010 to 1 from my first question)?
3) ad9361_pp_port_setup. What does the rx1rx2_phase_inversion_en do? In that part of the routine in the ad9361_pp_port_setup function, it writes to registers and bits that aren't described in the UG-671 register map.
ad9361_spi_writef(spi, REG_PARALLEL_PORT_CONF_2, INVERT_RX2, 1);
ad9361_spi_writef(spi, REG_INVERT_BITS, INVERT_RX2_RF_DC_CGOUT_WORD, 0);
The first write is to a bit which the guide says must be 0, and the address for the REG_INVERT_BITS is 0x189, which the register map just says must be 0x30. Do I need to set these as above in order to invert the LVDS lines, or can I leave all of that as is?