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Modifying axi_ad9361_dev_if to handle inverted data and clock lines on the AD9361

Question asked by BlakeM on Jan 27, 2015
Latest reply on Feb 3, 2015 by mhennerich

Hi, I'm using the AD9361 in LVDS mode on custom hardware. Several pairs of data and clock lines are inverted (the N signal is on the P pin and vice versa). It looks to me like the axi_ad9361_dev_if module is the place to modify the HDL to account for this?

 

I realize that it's not your job to fix my hardware, but if you have a minute to review the changes I made to compensate for the RX side of things, I would really appreciate it.

 

RX data clock is inverted:

 

At the end of axi_ad9361_dev.if.v, I commented out the following:

 

ad_lvds_clk #(

    .BUFTYPE (PCORE_DEVICE_TYPE))

  i_clk (

    .clk_in_p (rx_clk_in_p),

    .clk_in_n (rx_clk_in_n),

    .clk (l_clk));

 

and replaced it with:

 

signal clk_INVERTED;

 

IBUFGDS i_rx_clk_ibuf (

  .I (rx_clk_in_p),

  .IB (rx_clk_in_n),

  .O (clk_ibuf_s));


BUFG i_clk_gbuf (

  .I (clk_ibuf_s),

  .O (clk_INVERTED));


not(l_clk, clk_INVERTED);


So basically I just inserted a NOT gate after the clock buffer to invert the signal.

 

Similarly, all of the RX data lines are inverted, so I have modified line 243 to read:

 

always @(posedge l_clk) begin

  rx_data <= {rx_data_n_s, rx_data_p_s};

  rx_frame <= {rx_frame_n_s, rx_frame_p_s};

  rx_data_d <= rx_data;

  rx_frame_d <= rx_frame;

end

 

to read:

 

always @(posedge l_clk) begin

  rx_data <= {~rx_data_n_s, ~rx_data_p_s};

  rx_frame <= {rx_frame_n_s, rx_frame_p_s};

  rx_data_d <= rx_data;

  rx_frame_d <= rx_frame;

end


The resulting synthesized schematic in Vivado looks like I expect, but the digital tuning routine in the firmware fails, suggesting that the data is not being received by the HDL as I expect. Any advice you can provide would be very helpful. Thanks!

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