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Timing diagram question about AD9361

Question asked by zxu on Jan 23, 2015
Latest reply on Jan 30, 2015 by tlili

Hi everyone:

     I'm trying to configure out the timing diagram. I'm confused about that diagram on the reference manual. So I post the diagram up and wants so more specific explain about CMOS, FDD mode ,Dual port full duplex mode, 1r1t. The timing diagram posted below.


     I think that a rising edge of rx_frame indicates a start of frame so that I should capture data on the P0_D at rising edge and falling edge of data_clk and I could capture the IQ data separately of a frame.I exactly understand that frame can be set into different mode so that it will be different mode. But I just want to know about at which data_clk and rx_frame edge (or level ), I should capture the data on P0_D. I'm so confused because if capture data at rising edge of Data_clk and rx_frame should be high level, the timing diagram above dont even capture any data. Thanks for help.

Best Wishes