In table3 of AD7960 datasheet, there are two timing parameters tMSB and tCLKL. But there is no any information to explain how to slelect correct values for them. Should the maxiam values be OK? Or should some other rules must follow?
As long as you do not exceed these maximum values, it's fine. As stated in the datasheet, "After tMSB, elapses, the host begins to burst the CLK± signal to the AD7960...The required 20 CLK± pulses must finish
before tCLKL (referenced to the next conversion phase) elapses. Otherwise, the data is lost because it is overwritten by the next conversion result."
My understanding is: for tMSB a value is larger than the maxiam should be used, but for tCLKL, a value is smaller than the maxiam should be used. Is it correct?
My understanding is: for tMSB a value larger than the maxiam should be used, but for tCLKL, a value smaller than the maxiam should be used. Is it correct?
Both tMSB and tCLKL should not exceed the specified maximum value. Outside of the specs in the datasheet, we cannot guarantee part's performance.
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