We have completed the design of the four AD6654 based board having six TS201 DSP and it is in production.
Now we have another application in which we have to use multiple channels of a DDC (three channels per DDC ie 12 DDC channels)
The NCOs (centre frequency) of these DDC channels are spaces apart by 2 MHz .
All other register settings are same as filters are same.
The DDC frequency is 80 MHz and output frequency is 8 MHz (IQ outputs will come after every 125 ns).
Pclk is 100 MHz.
We are using soft sync.
We are using the SPI for DDC programming and enable and soft sync is repeated twice.
We are expecting that I0Q0, I1Q1 and I2Q2 should come consecutively after every 125 ns.
Each I / Q output will be available for 10 ns ie total 10 x 2 x 3 = 60 ns.
This is coming some time proper after DDC programming.
This time I0 , I1 , I2 values are same and Q0 , Q1 , Q2 values are same.
However sometime I2Q2 is coming after 30 ns after I1Q1 . Hence the total time is 90 ns.
This time I0 , I1 values are same and Q0 , Q1 values are same. However I2 and Q2 is different than I0I1 and Q0Q1 values.
We tried enabling
CH0 and CH1
CH1 and CH2
CH0 and CH2
Every time IQ is proper.
Attached is the screenshot in Xilinx ChipscopePro analyser.
One more observation is when NCO is programmed zero then the IQ sequence is proper and there is not time gap between I1Q1 and I2Q2.
This time I0, I1, I2 are same value and Q0,Q1,Q2 are zero or 0xFF.
I am attaching the .f4 and .svr file for your reference.
Only difference between the three DDC channel programming is we are using different NCO and MRCF control registers.
Please help us resolving this issue as we are stuck because of this issue.