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AD9129 - Delay Line Middle Set  vs  DLL Phase Offset

Question asked by GRL on Jan 22, 2015
Latest reply on Jan 26, 2015 by danf

What is the "Delay line middle set" value in register 0x0B, and how does it relate to / interact with the DLL "Phase offset" in reg 0x0A?  I'm sending parity bits alongside the data from my FPGA, so I can verify & monitor the interface.  By stepping reg 0x0A "phase offset" through all values within +-7, I get zero errors only with phase offset = -5 or -6.  Adjusting "delay line middle set", I see no effect at all.