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MDIO-read of PHY Regs bit-shifted to right 1-bit

Question asked by ShutEyeThinkin on Jan 22, 2015
Latest reply on Feb 11, 2015 by Aaronwu

Using bf537 with uClinux 2011R1-RC3.


I have a bf537 MDIO/MDC interface connected to a Micrel ksz8794 4-port Switch.


At boot-up, the Generic PHY driver reads from the PHY, at address 1, PHY Registers 2 and 3, to get the PHY_ID, which

for the ksz8794 is 0x0022.1550.


But, I am having a problem getting the PHY to stay up, and cannot send or receive pkts.


If I print the PHY_ID value read back from the PHY, it is 0x0011.0aa8, which is 0x0022.1550 shifted to the right 1 bit.

Reads of all the PHY registers are shifted to the right 1-bit.


Using a scope to examine the MDIO/MDC signals and timing, they look perfect. The proper registers are

being accessed, and the proper values are fetched, except they are bit-shifted.


The ksz8794 MDC is 2.5MHz, with a period of 400ns. The pull-up on MDIO is 4.7K, which Micrel suggested.


See attached MDIO/MDC signals and timing on a scope, showing the reading of PHY Register 3, which should return a value of 0x1550

(the reading of Reg 2, 0x0022)  is not shown). Also attached is the proper signals and timing to match the scope waveforms against.


Does anyone have any insight as to why the kernel's Generic PHY driver is reading this value as rightshifted 1-bit?