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TWI repeat start delay clears MEN bit

Question asked by dehkl on Nov 9, 2010
Latest reply on Nov 18, 2010 by PrasanthR


I am working with a repeat start (tx->rx) TWI transmission.When the cpu is busy I noticed that the Master Enable is cleared if some time (1ms or less) passes between setting the RSTART bit and handling the MCOMP interrupt request.

The problem is solved by setting the MEN bit at the same time the RSTART bit is cleared in the MCOMP handler.


Is this a known issue? The communication seems very stable with this fix but any improvements are appreciated.