I need to setup the AD9361 into LVDS mode and I am using the Noos software and ML605 HDL design as my base.Since I have my own data generate from FPGA, I have to modify the axi_ad9361.v and axi_ad9361_dev_if.v components in the AD6391 core.Since my data structure is 12-bits I Q,I have seen that in axi_ad9361_dev_if.v,there exits 12-bits data as follows:
dac_data_i1_s ; dac_data_q1_s ; dac_data_i2_s ; dac_data_q2_s ;
rx_data_i1 ; rx_data_q1 ; rx_data_i2 ; rx_data_q2 ;
So I make them out and cut down the origin connections.In the TX way,I connect my own data directly to the dac_data_i1_r and so on; In the rx,I directly get out the ra_data_i1 data.
Did I do the right ?
Should I change any other things?For example, the software side.
I have seen this discussion ,but I have no idea what I should do because it discusses the CMOS mode .Can you summarize how I should change the HDL design and the No-os Software If I want to transmit my own data in LVDS mode?
Wish your answer soon !