AnsweredAssumed Answered

adv7842 pixelclock (LLC) noise/glitch

Question asked by mbu on Jan 21, 2015
Latest reply on Apr 30, 2015 by GuenterL



We have an existing design with 4 adv7842 receivers. (RX1 -> RX4).


On RX1 do we have some problems with a noise/glitch on the LLC coming from adv7842.

This causes our back-end to clock in a "double-clock" pulse and the whole video-frame becomes corrupt.


This appear on "higher" pixelclock frequencies (above 130MHz).


We don't know why this appear and why it is only present on RX1 and not on the three "identical" inputs.


But it might be power-stability/grounding issues. We have sort of ruled out cross talk and reflections since the glitch is following the LLC rising edge, independent of frequency.


We have tried to avoid the problem by enabling LLC DLL in IO-register 0x19[7] and LLC_DLL_MUX in IO-register 0x33[6].

And then by adjusting the LLC_DLL_PHASE[4:0] in IO-register 0x19 we can move the glitch a bit up or down on the edge of LLC.


Register settings (IO map)

IO-register 0x19 = 0x9c

IO-register 0x33 = 0x40


In the attached HDMI_RX1_CLK_and_HDMI_RX1_HS.png you can see the glitch on the rising edge of the LLC which causes the problem.

(that measurement is with no LLC_DLL_MUX enabled)


We have been struggling with this and tried adjusting LLC_DLL_PHASE to shift the glitch out of the critical area but the whole issue is marginal and difficult to work with. Just attaching a probe may make the problem disappear.


Adjusting the drive strength in register IO-register 0x14 do not have an effect on the glitch and the current setting is 0x5d for LLC above 100MHz.


During this I accidentally set bit 0 and 1 in IO-register 0x33 and found that there seems to be some rise/fall or duty-cycle setting of the LLC related to these two bits ? (they are not described in manual)

See attached HDMI_RX1_CLK_REG_33_3.png where IO-register 0x33 = 0x3.


Do you have any suggestion on this ?


Have you seen similar cases before ?


Any help would be appreciated.