I am trying to use the AD 7366-5 A/D converter in conjunction with a Spartan 3E FPGA. This circuit was designed many years ago and has been primarily used to determine current polarity in power circuits in addition to other tasks. The usual frequency of these sinusoidal current signals is 60Hz and the purpose is to generate a logic 1 when current is positive and a logic 0 when the current goes negative. For a 60Hz signal, the circuit has performed very well all these years.
However, when I try to perform the same polarity detection with a 20kHz sinusoidal signal, I can see an appreciable delay of about 2uSec between the zero crossing of the analog signal and the time the digital signal goes from Low to High(or vice versa). The serial clock to the ADC is at 25MHz.
1. Is this delay to be expected and is it reasonable ? What parameters on the data sheet help determine this delay ?
2. If the application demands that this delay be as low as possible, what other options are available ?
3. Although not exactly pertaining to the above described problem, what is the correlation between the 'Throughput rate' and the maximum frequency of the analog signal that can be measured ? For instance, the Throughput rate for AD7366-5 is listed as 500kSPS. Does this mean that the maximum frequency of the analog signal that can be measured with this chip is 250kHz according to the Nyquist theory ?
Thank you for your time.