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Modifying HDL Design, FMCOMMS5 and ZC706

Question asked by tfabric on Jan 20, 2015
Latest reply on Mar 17, 2015 by MiTfreak

We are currently building a system based on the FMCOMMS5 and ZC706, with ADI reference HDL. We are able to build and customize our own Linux based on Analog Linux with AD9361 drivers etc. We also now see the "idea" of using libiio :-)


We have build our own (IP-core) processing module which is operating on IQ samples (internally it runs 200MHz), currently taking an AXI stream in and producing an AXI stream out. Now the question is where to brake up the working reference design. We started out skipping the pcore and analog-devices dma, thus modifying the Linux AD9361 drivers to only take care of the SPI interaction. In a sense we got a "analog free" (sorry) HDL. We then interconnected this with Xilinx "Axi Direct Memory Access" with scatter gather and "Axi Interconnect" to a slave AXI_HPx. This dataflow runs nice in a bare-metal supplication.

This though raised a couple of issues when using Linux, the Xilinx DMA driver is not libiio compatible, but we could build this our self or just couple to user-space in a more "conventional" way.

Another issue arose in the HDL, the way we synchronized the clock domains of the AD9361 ADC digital output and the FPGA-clock domain only work for low sample rates (we so to speak oversampled both the ADC clock, frame ad 6-bit data with a 400MHz FPGA clock). This issue have now turned us back to using the pcore "axi_ad9361".

We can also see that some of the procedures (which we disabled) in the AD9361 Linux driver could be to our (but we don't yet have the full insight) use.


So here are some question:

1: Which procedures are the AD9361 Pcore involved in ?

It seems like ADC sample clock adjustment is one of these and bias adjustment another.

2: Could you please name them all and make a short description of what they do, and which components are in action ?

3: In general does any of the calibration-procedures "taste" on the IQ samples on the Zynq processor, thus preventing us for modifying these in our own HDL processing module ?


Now the next question is, how do we most efficiently couple our processing module via DMA to the zynq processor and at best with libiio.

One solution could be a fifo after the PCORE to synchronize the ADC-clock domain and the FPGA-clock domain (as the AXI_DMAC_V1 does in you design). Followed by our own processing module (which eventually could be modified to standard fifo interface instead of AXI Stream for input) the output could then be fed to the  AXI_DMAC_V1 (this setup would not require two clocks in the AXI_DMAC_V1).

4: But does AXI_DMAC_V1 support Scatter Gather (SG) ?

5: and does the driver and libiio flow work with SG ?

6: Else if not using SG, what datarates could be attained with the DMA flow in the reference design ?

7: How would the dataflow work when the processing module is a kind of signal detector producing "burst" (In Xilinx streaming SG DMA we thought of using tlast for indicating "burst end-boundaries")

8: Is the Analog-Devices Pcore fifo interface compatible (timing wise etc) to the standard Xilinx Fifo interface ?


Another solution could be to couple the same fifo to the pcore and to a FPGA-clock domain, followed again by our processing module producing data into the Xilinx Streaming SG-DMA flow. And then eventual rewrite/construct a DMA-driver based on Xilinx DMA driver and Analog-devices iio interface to user space.


9: Which of the two do you believe will be the most efficient and have the most easy integration path ?


I think the subject and context is a little hard to describe in few lines, so maybe a discussion on the phone could be beneficial ?