We have designed our own board with the AD9361:
Using a single TX channel.
The RX channel is disabled (0x003=0x00).
DAC Clock : 122.88
Interface BBP:LVDS DDR
We get good and as expected Tx operation when the Tx channel is enabled, and interpolation filter in By-pass.
But when activating the hb1 interpolation filter, operations seems incorrect. We expect the data clock to be data clock/2.
But Data clock frequency stays constant regardless the filters configuration.
Test was done at lower BBPLL frequencies as well with same results.
I will appreciate a script or a guide for setting those filters correctly.