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Adv7842 Embedded syn problem

Question asked by Away.Liu on Jan 16, 2015
Latest reply on Jan 23, 2015 by GuenterL

Hi all:

     When i set 7842 vedio output embedded synchronous, some problem found, The Y embeded syn signal not agree with C embedded syn.

   the signal picture as follows show:

Catch(01-15-15-27-03).jpg

 

  Even i set free run or cap HDMI vedio signal ,the clk measured was correct,for ex:720P60 clk are 74.19MHz, But our receiver cannt recongnize the output vedio .

 

My configures are

 

    int err = 0;

    //"Device_adv7842InitSet_HDMI \n"

 

 

    err |= I2C0_reg_write(I2CADDR_ADV7842,0xFF,0x80); //reset

 

 

 

 

 

    //4 1.对寄存器地址编程

    err |= I2C0_reg_write(I2CADDR_ADV7842, 0xF1, SDP_I2C_address);      //SDP_I2C_address   

    err |= I2C0_reg_write(I2CADDR_ADV7842, 0xF2, SDPIO_I2C_address);    //SDPIO_I2C_address

    err |= I2C0_reg_write(I2CADDR_ADV7842, 0xF3, AVLINK_I2C_address);   //AVLINK_I2C_address

    err |= I2C0_reg_write(I2CADDR_ADV7842, 0xF4, CEC_I2C_address);      //CEC_I2C_address

    err |= I2C0_reg_write(I2CADDR_ADV7842, 0xF5, INFOFRAME_I2C_address);//INFOFRAME_I2C_address

    err |= I2C0_reg_write(I2CADDR_ADV7842, 0xF8, AFE_I2C_address );     //AFE_I2C_address

    err |= I2C0_reg_write(I2CADDR_ADV7842, 0xF9, REPEATER_I2C_address );//REPEATER_I2C_address

    err |= I2C0_reg_write(I2CADDR_ADV7842, 0xFA, EDID_I2C_address );    //EDID_I2C_address

    err |= I2C0_reg_write(I2CADDR_ADV7842, 0xFB, HDMI_I2C_address );    //HDMI_I2C_address

    err |= I2C0_reg_write(I2CADDR_ADV7842, 0xFD, CP_I2C_address );      //CP_I2C_address

    err |= I2C0_reg_write(I2CADDR_ADV7842, 0xFE, VDP_I2C_address );     //VDP_I2C_address

  

 

 

#if 1 // free run

    //4  3. auto graphic模式

  //  err |= I2C0_reg_write(I2CADDR_ADV7842,0x00,0x07);

   // err |= I2C0_reg_write(I2CADDR_ADV7842,0x01,0x02);//60HZ graphic mode

    //err |= I2C0_reg_write(I2CADDR_ADV7842,0x01,0x06);//60HZ graphic mode

   

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x00,0x02);

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x01,0x06);//60HZ graphic mode

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x02,0xF0);//default

    //err |= I2C0_reg_write(I2CADDR_ADV7842,0x02,0xF2);//RGB

 

 

 

     err |= I2C0_reg_write(I2CADDR_ADV7842,0x03,0x80);// 16-bit ITU-656 SDR mode 0 -->16bit

 

 

 

 

    #if 1 //4 freee Run设置

     err |= I2C0_reg_write(CP_I2C_address_1,0xBF,0x13);//force cp free run

     err |= I2C0_reg_write(CP_I2C_address_1,0xC9,0x2D);

 

      err |= I2C0_reg_write(CP_I2C_address_1,0x81,0xD0);// ; Set HDMI FreeRun enable

     

     //Disable the buffering of measured parameters in HDMI mode. Free run standard determined by PRIM_MODE[3:0], VID_STD[5:0] and V_FREQ[2:0]

       // err |= I2C0_reg_write(CP_I2C_address_1,0x07,0xFD);//embeded syn

   // err |= I2C0_reg_write(CP_I2C_address_1,0x13,0x03);//embeded syn

 

 

   // err |= I2C0_reg_write(CP_I2C_address_1,0x67,0x20);//embeded syn

  //  err |= I2C0_reg_write(CP_I2C_address_1,0x85,0x9B);//embeded syn

 

 

    #endif

    //4 不跑freerun   

#else

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x00,0x02);

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x01,0x06);// ; Prim_Mode =110b HDMI-GR

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x02,0xF4);// ; Auto input color space, Limited Range YPbPr Output

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x03,0x82);//; 24-bit ITU-656 SDR mode 0 -->16bit

#endif

 

 

    #if 1

    printf("test000!\n");

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x04,0x62);// default :Output bus rotation

 

 

  

   // err |= I2C0_reg_write(I2CADDR_ADV7842,0x05,0x28);// ; AV Codes Off

    /*如果使用内嵌同步信号的话,需要时能AVCODE_INSERT_EN, Addr 40(IO), Adress 0x05[2]=1

     Insert AV codes into data stream.*/

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x05,0x2C);// ; AV Codes Off

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x06,0xA6);// ;

   

 

    #if 1

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x0C,0x40);// ; Power up part and power down VDP

   

   // err |= I2C0_reg_write(I2CADDR_ADV7842,0x15,0x80);// ; Disable Tristate of Pins

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x15,0x85);// ; Disable Tristate of Pins

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x19,0x83);// ; LLC DLL phase

    err |= I2C0_reg_write(I2CADDR_ADV7842,0x33,0x40);// ; LLC DLL enable

    #endif

 

 

 

 

 

 

 

 

 

    printf("test111!\n");

    err |= I2C0_reg_write(HDMI_I2C_address_1,0xC0,0x00);// ; HDMI power control (power saving)

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x0D,0x34);// ; ADI recommended write

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x3D,0x10);// ; HDMI ADI recommended write

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x44,0x85);// ; TMDS PLL Optimization

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x46,0x1F);// ; ADI Recommended Write ES3/Final silicon

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x57,0xB6);// ; TMDS PLL Optimization

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x58,0x03);// ; TMDS PLL Setting

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x60,0x88);// ; TMDS PLL Optimization

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x61,0x88);// ; TMDS PLL Optimization

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x6C,0x18);// ; Disable ISRC clearing bit, Improve robustness

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x75,0x10);// ; DDC drive strength

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x85,0x1F);// ; ADI Equaliser Setting

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x87,0x70);// ; HDMI Recommended write

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x89,0x04);// ; ADI Equaliser Setting

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x99,0xA1);// ; HDMI ADI recommended write

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x9B,0x09);// ; HDMI ADI recommended write

   

    #if 1

    err |= I2C0_reg_write(HDMI_I2C_address_1,0xC1,0xFF);// ; HDMI power control (power saving)

    err |= I2C0_reg_write(HDMI_I2C_address_1,0xC2,0xFF);// ; HDMI power control (power saving)

    err |= I2C0_reg_write(HDMI_I2C_address_1,0xC3,0xFF);// ; HDMI power control (power saving)

    err |= I2C0_reg_write(HDMI_I2C_address_1,0xC4,0xFF);// ; HDMI power control (power saving)

    err |= I2C0_reg_write(HDMI_I2C_address_1,0xC5,0x00);// ; HDMI power control (power saving)

    err |= I2C0_reg_write(HDMI_I2C_address_1,0xC6,0x00);// ; HDMI power control (power saving)

     

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x01,0x18);// ; Enable clock terminators

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x1A,0x8A);// ; Unmute audio

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x67,0x20);// ; TMDS PLL Setting

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x8A,0x1E);// ; ADI Equaliser Setting

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x93,0x04);// ; ADI Equaliser Setting

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x94,0x1E);// ; ADI Equaliser Setting

    err |= I2C0_reg_write(HDMI_I2C_address_1,0x9D,0x02);// ; ADI Equaliser Setting

    //err |= I2C0_reg_write(HDMI_I2C_address_1,0xC9,0x01);// ; HDMI free Run based on PRIM_MODE, VID _STD

    #endif

 

 

 

 

  

    printf("test222!\n");

    err |= I2C0_reg_write(AFE_I2C_address_1,0x00,0xFF);// ; Power Down ADC's and there associated clocks

    err |= I2C0_reg_write(AFE_I2C_address_1,0x01,0xFE);// ; Power down ref buffer_bandgap_clamps_sync strippers_input mux_output buffer

   //  err |= I2C0_reg_write(AFE_I2C_address_1,0xB5,0x01);//; Setting MCLK to 256Fs

 

 

    err |= I2C0_reg_write(CP_I2C_address_1,0x3E,0x00);// ; Disable CP Pregain Block

    err |= I2C0_reg_write(CP_I2C_address_1,0xBA,0x01);// ; Set HDMI FreeRun enable

 

    //err |= I2C0_reg_write(CP_I2C_address_1,0x6C,0x00);// ; Use fixed clamp values

  

 

 

 

 

  

   // #if 0  //--------start //此段设置导致9132还回出现问题

   //err |= I2C0_reg_write(HDMI_I2C_address_1,0x00,0x3F);// ; Set HDMI Input Port B (Enable BG monitoring)

    // ---------end //此段设置导致9132还回出现问题

 

 

    #endif

 

 

    PRINTK_DEBUG(gPriLevel, "Device_adv7842InitSet_HDMI __finished\n");

    

    return err;

Outcomes