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ADV7513 @ 1080p is washed out

Question asked by mferraro on Jan 15, 2015
Latest reply on Jan 30, 2015 by GuenterL

I have a design that receives HDMI via ADV7611, feeds into Artix 7 FPGA the splits the video stream to three monitors SDI , HDMI and VGA.

The VGA monitor is driven by ADV7125

The HDMI monitor is driven by ADV7513

(see attached block diagram, there are actually multiple channels)

 

At 720p60; everything looks great

At 1080p60; the VGA’s look great but the HDMI looks terrible.

The HDMI seems be washed out; with lots of light green outlines to everything. 

(I've tried to snap pictures; but they don't really show the effects well)

 

Some thoughts

[1] Poor timing on the output from the FPGA

[2] Some registers settings that aren’t good for 1080p60

[3] Crappy cable

 

Here is my sequence.

I’m expecting video that is RGB 24 bit 4:4:4 SDR

 

Register Settings for ADV7513

 

controlRegWrite(baseaddr, i2cAddr, 0x41, 0x10); //00010000

controlRegWrite(baseaddr, i2cAddr, 0x98, 0x03); //                   // Must be set to 0x03 for proper operation

controlRegWrite(baseaddr, i2cAddr, 0x9A, 0xE0); // 0x9A[7:5] = 0b111   // Must be set to 0b1110000

controlRegWrite(baseaddr, i2cAddr, 0x9C, 0x30); // 0x9C = 0x30         // Must be set to 0x30 for proper operation

controlRegWrite(baseaddr, i2cAddr, 0x9D, 0x01); // 0x9D[1:0] = 0b01    // 1:0 must be set to 01 for proper op. 3:2 sets clock divider

controlRegWrite(baseaddr, i2cAddr, 0xA2, 0xA4); // 0xA2 = 0xA4      // Must be set to 0xA4 for proper operation

controlRegWrite(baseaddr, i2cAddr, 0xA3, 0xA4); // 0xA3 = 0xA4     // Must be set to 0xA4 for proper operation

controlRegWrite(baseaddr, i2cAddr, 0xE0, 0xD0); // 0xE0[7:0] = 0xD0   // Must be set to 0xD0 for proper operation

controlRegWrite(baseaddr, i2cAddr, 0xF9, 0x00); // 0xF9[7:0] = 0x00   // Must be set to 0x00 for proper operation

 

Any ideas on things to test or change would be appreciated

 

Thanks,

 

Matt

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