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a AD9361 timing problem

Question asked by yzg931228 on Jan 15, 2015
Latest reply on Jan 15, 2015 by yzg931228

I am using the AD-FMCOMMS3-EBZ and have a problem.

I use the LVDS mode.

The picture 1 is the data path functional timing in AD9361 Reference Manual.

The picture 2 is my design showed by vivado hardware manager.

The arrow points to the data_clk which is different from the AD9361 Reference Manual.

So what's the problem in my design ?

thank you!

QQ截图20150115153027.png

QQ截图20150115153439.png

 

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