I am trying to use the AD-FMCJESDADC1-EBZ with a ZC706 board. I have successfully run through the reference design (www.wiki.analog.com/resources/fpga/Xilinx/fmc/ad-fmcjesdadc1-ebz), but this design was done with EDK. I am trying to port this design to Vivado. To make things easier, I am starting by only trying to communicate with the FMC board via the SPI interface. I modified the reference design software to read a register on the AD9250, print it to the terminal, write a different value to that register, then read it again, and print the new value to be sure that it was changed. This works fine when I use the bitfile from the reference design. However, when I use my own design that only contains the processing system cores, and the SPI and util_cpld cores (imported from the reference design) it does not appear to be talking to the FMC board. I have also tried this with Xilinx's Quad_SPI core that is available in Vivado, but I get the same results.
Before I waste any more time debugging this, I wanted to ask if there was an existing Vivado project for the AD-FMCJESDADC1_EBZ with the ZC706 as the carrier, available from Analog devices (or anyone else)?
If there is not an existing project, is there any reason that the reference design cores would not work with the ZYNQ processor cores in Vivado? I am able to import the cores (as per Xilinx documentation), and generate a bitstream with no errors. I just can't seem to communicate with the FMC board.