The ZC706 has 4 GTX lines (lanes) going across the FMC connector. This means on the DAQ2 board two lanes are used for ad9680 and two lanes for the ad9144.
Is it possible to use the dual link mode on the ad9144 - this would be lane 0 and lane 4?
When Xilinx talks about "lanes", they do not mean "lines", they mean "Tx/Rx pair".
8 GT, means 8 high speed pair, so I don't know where you got "4" from.
AD9680 connects to the Rx GT lines.
AD9144 connects to the Tx GT lines.
As Rejeesh says, this is documented in all the schematics/manuals.
Please read the DAQ2 user guide also look at the schematics of ZC706 and DAQ2.
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