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BF592 SPI0 interrupt

Question asked by spetca on Jan 14, 2015
Latest reply on Mar 11, 2015 by jobo23

Trying to get an interrupt after loading SPI0_TDBR register, I only get to the EX_INTERRUPT_HANDLER at ssync(); after the SPI enable instruction. Cannot get it to interrupt after loading the Tx buffer...?

 

 

 

#include <ccblkfn.h>

#include <bfrom.h>

#include <stdio.h>

#include <sys/exception.h>

#include <cdefBF592-A.h>

#include <cdef_LPBlackfin.h>

#include <defBF59x_base.h>

 

void InitPorts(void);

void InitSPI(void);

void SPI_Tx_Write(u16 data);

void SPI_Rx_Read(u16 address);

void Init_Interrupts(void);

 

EX_INTERRUPT_HANDLER(SPI0_ISR);

 

void main()

{

 

  Init_PLL();

  InitPorts();

  Init_Interrupts();

  InitSPI();

SPI_Tx_Write(0xAFAF);

 

}

 

 

 

void Init_PLL(void)

{

  u32 SIC_IWR1_reg;                /* backup SIC_IWR1 register */

 

 

  /* use Blackfin ROM SysControl() to change the PLL */

    ADI_SYSCTRL_VALUES sysctrl ={ VRCTL_VALUE,

                                                          PLLCTL_VALUE,

                                                          PLLDIV_VALUE,

                                                          PLLLOCKCNT_VALUE,

                                                             PLLSTAT_VALUE };

 

  /* use the ROM function */

  bfrom_SysControl( SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_VRCTL  , &sysctrl, NULL);

  ssync();

}

 

 

void Init_Interrupts(void)

{

 

  register_handler(ik_ivg10, SPI0_ISR);

  *pSIC_IMASK0 |= IRQ_DMA5;

  *pIMASK |= 0x40F;

  ssync();

}

 

 

 

void InitSPI()

{

 

  //SPI Port Setup//////////////////////////////

  // First Set PORTF_MUX registers

  *pPORTF_MUX |= 0x300;

 

  // Set PORTx_FER registers

  *pPORTF_FER |=  0xe300;

 

  // Set PORTxIO_DIR registers

  *pPORTFIO_DIR = 0xff;

 

  // Set PORTxIO_INEN registers

  *pPORTFIO_INEN |= 0x0;

  *pPORTGIO_INEN |= 0xff00;

  ssync();

  ///////////////////////////////////////////////

 

 

 

  *pSPI0_FLG |= FLS3 ;

  *pSPI0_FLG |=  ~FLG3;

  *pSPI0_BAUD = 500;

  *pSPI0_CTL |= TDBR_CORE | EMISO | SIZE | MSTR | CPHA | CPOL ;

  *pSPI0_CTL |= SPE;

  ssync();

 

}

 

 

void SPI_Tx_Write(u16 data)

{

  *pSPI0_FLG ^=  FLG3;

  *pSPI0_TDBR = 0x0010;

  *pSPI0_TDBR = data; //load address into Tx buffer, writing to TDBR kicks off SPI transfer

  *pSPI0_FLG ^=  FLG3;

 

}

 

 

 

EX_INTERRUPT_HANDLER(SPI0_ISR)

{

 

  *pSPI0_FLG    ^= FLG3;        //toggle csb pin

  *pSIC_IMASK  &= ~IRQ_DMA5;

  ssync();

}

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