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AD9361 LVDS DATA_CLK

Question asked by Ed_V Employee on Jan 13, 2015
Latest reply on Jan 14, 2015 by tlili

Hello,

 

We are using the AD9361; the DATA-CLK signal from this part drives a Xilinx 7030 FPGA. We broke out a test point to monitor both sides of the DATA-CLK signal. The main DATA-CLK signal path from the AD9361 to the FPGA is all routed on the same layer, but the test point is routed to a surface layer by way of a couple of vias, the attached diagram shows the trace lengths.

 

We probe DATA-CLK with solder-in, differential ZIF tips using an Agilent DSA. We’re seeing non-monotonic rise/fall times on the signal

(see attachment), but the transceiver is operating correctly.

 

Is it possible this waveform looks fine at the FPGA, but it’s distorted at the stub probe-point? (Unfortunately we can’t probe the FPGA
pins.) Can you offer any suggestions or recommendation?

 

We tried reducing the rise/fall times by programming register 0x03B [D5:D4] to “11” but it didn’t appear to change anything.

 

Thanks

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