AnsweredAssumed Answered

slow reads from 21489 SDRAM?

Question asked by ravedave on Jan 13, 2015
Latest reply on Jan 23, 2015 by AlClark

I'm using a 21489 @ 400 MHz with a standard SDRAM (Alliance AS4C16M16S-6TCN). Just using bank zero, and it works fine, no errors. The problem is while writes are fast (consistently around 20 nsec, the reads are minimum 60 nsec and jump up to 150 nsec. I would think it's a setup issue, except the writes are fine. Tried a number of things, but no improvements. Below is PLL and SDRAM init code.Hoping it's something simple, thanks!


int i, pmctlsetting, cs_temp;



    pmctlsetting = PLLM50 | SDCKR2_5 | DIVEN;// set bits as required400 MHz w/ PLLM50

    *pPMCTL= pmctlsetting;



    pmctlsetting|= PLLBP;// Setting the Bypass bit
    pmctlsetting^= DIVEN;// Clearing the DIVEN bit - has to be done while bypass is on
    *pPMCTL= pmctlsetting;// Putting the PLL into bypass mode - has to be done when changing the VCO/PLL



    for (i=0; i<5000; i++)    // Wait for around 4096 cycles for the pll to lock.



   pmctlsetting = *pPMCTL;
pmctlsetting ^= PLLBP;      // Clear Bypass Mode
*pPMCTL = pmctlsetting;// DIVEN does not need to be set again aparently



    for (i=0; i<16; i++)    // Wait for around 15 cycles for the output dividers to stabilize.

     // Mapping Bank 0 to SDRAM   


    *pEPCTL |= B0SD;


*pSDRRC  =  0x00004d8;   


    //Programming the SDCTL register



    cs_temp = *(volatile int*) 0x200000;// dummy read