My colleague and I have brought up the ZC702 / AD-FMCOMMS4 evaluation boards using the No OS HDL options. We successfully ran the steps listed in the Wiki, though the final waveform we see in the Vivado environment, though periodic, does not look like a sine wave. It appears that the sine wave look up table used to generate the modulation input to the transmitter is using 8 bit magnitude values, with the upper four bits acting as sign bits for twos complement numbers. However, it also looks like, in the block diagram, the connection to the AD9364 is utilizing the input to the TX data path in the LVDS mode, such that there are only six bits of information that can be written to the device. We are currently re-scaling the sine wave look up table to six bits to see if this fixes the issue.
Question 1: Has something changed since the creation of the No-OS implementation example that has broken the data stream in some way, such that a sine wave is no longer produced at the receiver?
A bigger issue for us is trying to determine how to modify the sample design (Block diagram, Verilog, and C Code) to begin customizing the design with new features. Looking at the Verilog code, it appears as if all of the Verilog has been generated from a software tool, such as, perhaps, Xilinx HDL Generator. We cannot find any reference to such source files.
Question 2: For the uninitiated (this is our first exposure to the ZC702 platform), are there source files in another platform, e.g., Matlab, and are they available for download that are used to implement the No-OS example? If so where? And if so, what specific Matlab toolboxes are needed to use the source files and produce new files that can be moved to the Vivado environment?
Question 3: If the source files for the ZC702 / AD-FMCOMMS4 design were all generated within Vivado, are there any examples of new features added to the sample design?
Thanks in advance,