I have a customer with the following questions:
Is the Full Scale Input fixed at 1.2Vpp or is it adjustable?
Does SPI_VDDIO have to be +2.5V as indicated on page 4 of the datasheet? Eval Board looks like it is hooked up to +3.3V, we would like to use +1.8V in our design.
Does VDDIO have to be +2.5V as indicated on page 4 of the datasheet? Eval Board looks like it is hooked up to +3.3V, we would like to use +1.8V in our design.
The datasheet says nothing about VP_BYP except ‘Voltage Bypass’. Eval board schematic has a 0.1uF capacitor with stuffing option for this pin to be connected to DRVDD_1P2V. Should we have the same circuit in our design or can more information be provided regarding this pin?
The datasheet says nothing about VM_BYP except ‘Voltage Bypass’. Eval board schematic has a 0.1uF capacitor. Should we just copy the Evaluation Board?
Eval Board schematic power nets say ‘AVDD_1P2V’, ‘DRVDD_1P2V’ and ‘DVDD_1P2V’ even though datasheet says 1.3V. I am assuming these are just incorrect net names and the voltage is really 1.3V?
While the datasheet does explain to hook them up with a ‘10K Ohm resistor to GND’, the datasheet does not explain what functions REXT and RBIAS_EXT serve?
What is the polarity of the PWDN bit? The datasheet does not say.
Why does the datasheet define VCM as an output in the Pin Function table (Table 8) and then right next to the word ‘Output’ call it an ‘Analog Input’?
SYNCINB+/- are inputs to the device (page 12 of the datasheet) but are shown as outputs on the Eval schematic (page 9 of 9)?
Is a 100 Ohm termination needed on the SYNCINB+/- input to the device?
Does the SPI bus need any pull-ups or pull-downs?
ADC_DRVDD13 has only two bypass caps on the Eval board but has seven pins on the device, are two bypass caps sufficient for this rail? All of the other power groups have one bypass cap per pin.
Would it be okay to supply the DRVDD_2P5, DVDD_2P5, DVDD_IO and SPI_DVDD_IO with independently filtered versions of our main +2.5V supply or is it recommended/required to power these rails from dedicated ADP125 LDO’s as shown in Figure 86?