My customer has the following questions:
In Figure 148, would 100nF work where the 2.4nF AC coupling caps are shown?
Do DCI_P/DCI_N, FRM_P/FRM_N and PxDxP/Px_DxN all have internal 100 Ohm termination resistors?
What is the common mode voltage of the LVDS receivers on the device?
Datasheet states on page 11 to pull up IRQ line with a 1K resistor then says on page 47 to pull up IRQ with a 10K resistor, which one is it? 1K or 10K?
VSSA has no bypass capacitors on the Evaluation Board. Does this mean that my design does not need them either?
Why does the Evaluation Board have a split power plane on Layer 2 of the PCB (DVDD and AVDD)? Wouldn’t a solid GND plane be the best function for Layer 2?
Does the SPI bus need any pull-ups or pull-downs?
Is it okay to use a charge pump (MAX1673ESA+) to produce the -1.5V power rail?