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SPI clock phase for talking to ADXL375

Question asked by Benp on Jan 6, 2015
Latest reply on Jan 6, 2015 by neilzhao

I am using an STM microcontroller to talk to the ADXL375 digital accelerometer using SPI.

The SPI signal timing diagram for the accelerometer is illustrated in the attached figure for reference.


I'd like some guidance on the SPI clock settings for the uC.

Looking at the diagram, it is clear that the spi clock polarity should be high (1).

I'd not sure about the setting for the spi clock phase.


The data output by the uC is latched by the accelerometer in the second (rising) edge. So to honor the required setup time, I am thinking that the uC should send SPI data out at the first (falling) edge.

But I am wondering if this would mess up the timing for SDI sampling, because bit D7 is not ready by the falling edge of clock for the eighth bit (immediately following A0).


Any clarification is appreciated.