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HMC649LP6E Control Voltage spec.

Question asked by sss on Jan 4, 2015
Latest reply on Feb 1, 2015 by sss



This is the first time for checking the Hittite device ,digital phase shifter.

Please advise to me.


In the datasheet,HMC649LP6E control voltage specification is following.


Control Voltage

State Bias Condition

Low (0):0 to 0.2 Vdc

High (1):Vdd ±0.2 Vdc @ 35 μA Typ. >>> 5.0V±0.2V


I supply to the control voltage input from the FPGA.

Output voltage from FPGA is not match for control voltage specification.

It is a tight tolerance on the control voltage input level !!!


Does this device need to level shift circuits ?

Will you provide recommended Logic interface circuit?


Typical reference level is following

FPGA is same spec.

CMOS level (V)

Hi level input : 0.7×Vdd

Low level input : 0.2×Vdd

Hi level output : Vdd-0.8

Low level output : 0.4