I'm trying to understand the TX part of FPGA DAQ2 design (ZC706). The reason for the following questions is because we would like to replace the Tx generator with our own design, by just applying data to the tx_data(127:0) every tx_clk cycle.
Here the axi_daq2_gt output the tx_clk_g clock going to the Xilinx core JES204. I assume the tx_core_clk requires to be 156,25MHz (with the 4 lane configuration).- is this the speed or?
I'm no Verilog expert and find it difficult to find the source to the tx_clk_g? What is the tx_clk_g source, external and going through which modules?
Can the clock speed be changed and with which registers are this done?