I have designed a PCB with Altera Cyclone IV GX FPGA, ADI's AD7626 ADC and some other components. I used ADP5024 regulator for powering the FPGA. I followed the recommendations given by the following document:
I am using the first buck (VOUT1) to derive 1.2V for the core voltage, and second buck (VOUT2) to derive 2.5V for the IO. The LDO (VOUT3) is being used for the PLL analog supply (2.5V). I have followed all the recommendations and chosen the resistor values appropriately. The input supply is 3.3 V from the motherboard PCIe slot. Unfortunately, after powering up, I am seeing strange behaviors:
VFB1 ~ 1.2V!!!
VFB2 ~ 0.7V!
VFB3 ~ 0.7V!
VOUT1 ~ 1.2V (in spite of misbehavior with VFB1!!!!)
VOUT2 ~ 3.3V
VOUT3 ~ 3.3V
According to the datasheet, VFB should be 0.5V, but I am stunned by this strange behavior. Does this happen when the load is heavy. I have just created a design with single flip-flop inside the FPGA (just to test the behavior after power-up). Fortunately, the FPGA is working fine, but I am really at a loss of words to understand the behavior of the regulator. I have physically measured the values of the resistors, and they are the same as I worked out using the formula given in the datasheet.
Can someone provide me some tips as to what may be the issue. I am attaching the schematic for reference.