If we set the DEF_VAL_EN bit in 0x0C register, the SDP will only output the default value. So in this mode, can we modify the output HS/VS synchronization signals? Thanks.
We are currently on a shutdown and support is limited so I will try to answer your question as best I can. The DEF_VAL_EN bit allows the manual forcing of free-run with the color determined by the DEF_Y and DEF_C values for YCbCr. I need to get clarification on what the output timing depends on when in this mode and whether the H/V signals can be output and/or modified.
Can you please detail which HS and VS controls you want to use when forcing the SDP into free run mode by setting DEF_VAL_EN to 1? Do you want to change the polarity only, or do want to change the begin and end positions?
Thanks for your answers. Yeah, we need to change the HS/VS begin/end positions when setting DEF_VAL_EN to 1. Can we?
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